The Cadence® OrCAD®FPGA System Planner addresses the challenges that engineers encounter when designing one or more large pin-count FPGAs on the printed circuit board—which include creating the initial pin assignment, integrating with the schematic, and ensuring the device is routable on the board. It shortens the time required to design-in complex, large pin-count FPGAs by allowing entry of design intent at the system level and then completely automating the pin assignment over multiple FPGAs at once, greatly reducing the risk of manual error. This solution reduces the number of pin optimization iterations during PCB layout and minimizes the number of layers required to route the FPGA on a PCB design.
The OrCAD FPGA System Planner comes with an FPGA device library to help with selection of devices to be placed. It uses Cadence OrCAD and Allegro PCB Editor footprints for the floor plan view and allows users to quickly create relative placement of the FPGA system components. Users are allowed to specify connectivity between components within the FPGA sub-system through interface definitions, saving time to plan FPGAs into a system. They can create interfaces such as DDR2, DDR3, and PCI Express, and use these to specify connectivity between a FPGA and a memory DIMM module or between two FPGAs. The OrCAD FPGA System Planner understands differential signals and power signals, as well as clock signals.
The OrCAD FPGA System Planner comes with a library of device-accurate FPGA models that incorporate pin assignment rules and electrical rules specified by FPGA device vendors. These FPGA models are used by the FPGA I/O synthesis engine to ensure that the vendor-defined electrical usage rules of the FPGAs are strictly adhered to. These rules dictate such things as clock and clock region selection, bank allocation, SSO budgeting, buffer driver utilization, I/O standard voltage reference levels, etc. During synthesis, the OrCAD FPGA System Planner automatically checks hundreds of combinations of these rules to ensure the FPGA pins are optimally and accurately utilized.
The OrCAD FPGA System Planner provides users a way to create a FPGA system placement view using OrCAD and Allegro PCB Editor footprints. Users specify connectivity between components in the placement view and the FPGA at a high level using interfaces such as DDRx, PCI Express, SATA, Front Side Bus, etc. that connect FPGAs and other components in the design, shortening the time to specify design intent for the FPGA system. Once the connectivity of the FPGA to other components in the sub-system is defined, the product synthesizes the pin assignment based on the user’s design intent, available FPGA resources, component placement around the FPGA, and the FPGA vendor’s pin assignment rules.
The OrCAD FPGA System Planner has a built-in DRC engine that incorporates the rules provided by FPGA vendors for pin assignment, reference voltages, and terminations. This rules-based engine prevents PCB physical prototype iterations, as the FPGAs are always correctly connected. Pin assignment algorithms are optimized to assign interface signals to a group of pins, minimizing net crossovers and improving routability on the PCB.
In addition to its integration with Cadence OrCAD PCB design technologies, the OrCAD FPGA System Planner communicates seamlessly with FPGA design tools, generating and reading supported FPGA vendors’ pin assignment constraint files. This capability enables the FPGA designer to evaluate pin assignments against the functional needs of the FPGA. Any changes made by the FPGA designer to account for these requirements can be imported into to the tool so that the complete set of pin assignments remains in sync. With this integration, users can also import pin assignments into the OrCAD FPGA System Planner for a design started with the FPGA tools to validate assignments with other components in a placement view.
Architecture supported:
- Altera®
- Stratix® II
- Stratix II-GX
- Stratix III - GX
- Stratix IV
- Xilinx®
- CoolRunner™ II
- CoolRunner XPLA3
- Spartan®-3
- Spartan-3A
- Virtex®-4
- Virtex-5
- Scalable, cost-effective FPGA PCB co-design solution for the OrCAD PCB Design technologies
- Shortens time for optimum initial pin assignment, accelerating PCB design schedules
- Accelerates integration of FPGAs with Cadence OrCAD PCB design creation environment
- Eliminates unnecessary, frustrating design iterations during the PCB layout process and physical prototype iterations due to FPGA pin assignment errors
- Reduces PCB layer count through placement aware pin assignment and optimization
- Helps designers do cost and performance trade-offs quickly, enabling architectural exploration that is not practical with manual approaches.
- Shortens the time it takes for designers to get to the ASIC prototype using FPGAs
- Communicates seamlessly with FPGA vendor design tools
- Optimize FPGA pin assignment after placement and during routing of the interfaces and signals on a FPGA